Tracking multiple dependent instructions with instruction...

Details Tracking multiple dependent instructions with instruction... Tracking multiple dependent instructions with instruction...

2006-10-02

2008-12-09

Kim, Kenneth S (Department: 2111)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

C712S214000

Reexamination Certificate

active

07464253

ABSTRACT:
A method and apparatus for improving the operation of an out-of order computer processor by utilizing and managing instruction wakeup using pointers with an instruction queue payload random-access memory, a mapping table, and a multiple wake-up table. Instructions allocated to the instruction queue are identified by association with a physical destination register used to index in the mapping table to provide dependent instruction information for instruction wakeup for scalable instruction queue design, reduced power consumption, and fast branch mis-prediction recovery, without the use of content-addressable memory cells.

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D. Folegnani and A. González, “Energy Effective Issue Logic”, Procs. 28th Intl. Symposium on Computer Architecture, 2001. pp. 230-239.

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