Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
Reexamination Certificate
2005-12-13
2008-10-07
Huisman, David J (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Scoreboarding, reservation station, or aliasing
Reexamination Certificate
active
07434032
ABSTRACT:
A scoreboard memory for a processing unit has separate memory regions allocated to each of the multiple threads to be processed. For each thread, the scoreboard memory stores register identifiers of registers that have pending writes. When an instruction is added to an instruction buffer, the register identifiers of the registers specified in the instruction are compared with the register identifiers stored in the scoreboard memory for that instruction's thread, and a multi-bit value representing the comparison result is generated. The multi-bit value is stored with the instruction in the instruction buffer and may be updated as instructions belonging to the same thread complete their execution. Before the instruction is issued for execution, this multi-bit value is checked. If this multi-bit value indicates that none of the registers specified in the instruction have pending writes, the instruction is allowed to issue for execution.
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patent: 7093106 (2006-08-01), Ambekar et al.
patent: 2004/0024993 (2004-02-01), Pathasarathy
patent: 2003-35589 (2003-05-01), None
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English abstract of JP 2003-35589 with additional translated information.
Translated Japanese Office Action dated Jun. 9, 2008 (provided as an explanation of relevance of Citation No. B1.
Coon Brett W.
Mills Peter C.
Oberman Stuart F.
Siu Ming Y.
Huisman David J
NVIDIA Corporation
Patterson & Sheridan L.L.P.
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