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SIMD datapath coupled to scalar/vector/address/conditional...

Electrical computers and digital processing systems: processing – Processing architecture – Array processor
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SIMD microprocessor, image processing apparatus including...

Electrical computers and digital processing systems: processing – Processing architecture – Array processor
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SIMD operation method and SIMD operation apparatus that...

Electrical computers and digital processing systems: processing – Processing architecture – Array processor
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SIMD operation system capable of designating plural...

Electrical computers and digital processing systems: processing – Processing control – Processing control for data transfer
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SIMD processor executing min/max instructions

Electrical computers and digital processing systems: processing – Processing control
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SIMD processor executing min/max instructions

Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
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SIMD processor with concurrent operation of vector pointer...

Electrical computers and digital processing systems: processing – Processing architecture – Array processor
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SIMD processor with scalar arithmetic logic units

Electrical computers and digital processing systems: processing – Processing architecture – Array processor
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SIMD system having logic units arranged in stages of tree struct

Electrical computers and digital processing systems: processing – Processing architecture – Array processor
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SIMD/MIMD processing synchronization

Electrical computers and digital processing systems: processing – Processing architecture – Array processor
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Simple algorithmic cryptography engine

Electrical computers and digital processing systems: processing – Instruction fetching
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Simple branch prediction and misprediction recovery method

Electrical computers and digital processing systems: processing – Processing control – Branching
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Simple load and store disambiguation and scheduling at...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Simple load and store disambiguation and scheduling at...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Simplified method to generate BTAGs in a decode unit of a...

Electrical computers and digital processing systems: processing – Processing control – Branching
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Simulated memory stack in a stackless environment

Electrical computers and digital processing systems: processing – Architecture based instruction processing – Stack based computer
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Simultaneous multi-thread instructions issue to execution...

Electrical computers and digital processing systems: processing – Instruction issuing
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Simultaneous parity generating/reading circuit for massively par

Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Patent

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Simultaneous speculative threading light mode

Electrical computers and digital processing systems: processing – Processing control
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Simultaneously assigning corresponding entry in multiple...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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