Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2005-01-04
2005-01-04
Kim, Kenneth S. (Department: 2111)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S003000, C712S022000, C713S324000
Reexamination Certificate
active
06839828
ABSTRACT:
There is provided a processor designed to operate in a plurality of modes for processing vector and scalar instructions. Register files are each for storing scalar and vector data and address information. A parallel vector unit, coupled to the register files, includes functional units configurable to operate in a vector operation mode and a scalar operation mode. The vector unit includes an apparatus for tightly coupling the functional units to perform an operation specified by a current instruction. Under a vector operation mode, the vector unit performs, in parallel, a single vector operation on a plurality of data elements. The operations performed on the plurality of data elements are each performed by a different functional unit of the vector unit. Under a scalar operation mode, the vector unit performs a scalar operation on a data element received from the register files in a functional unit within the vector unit.
REFERENCES:
patent: 4748585 (1988-05-01), Chiarulli et al.
patent: 5423051 (1995-06-01), Fuller et al.
patent: 5758176 (1998-05-01), Agarwal et al.
patent: 5778241 (1998-07-01), Bindloss et al.
patent: 6192467 (2001-02-01), Abdallah et al.
patent: 6195746 (2001-02-01), Nair
M. Tremblay et al. “VIS Speeds New Media Processing”, IEEE Micro,Aug. 1996 pp. 10-22.
R. Lee, “Multimedia Enhancements for PA-RISC Processors” Hewlett-Packard Company, HotChips VI, 8/94 pp. 7.3.1-7.3.10 (183-191).
K. Diefendoroff et al. “How Multimedia Workloads Will change Processor Design”, Computer, Sep. 1997 pp. 43-45.
T. M Conte et al. “Challenges to Combining General-Purpose and Multimedia Processors” Dec. 1997, Computer IEEE pp. 33-37.
R. B. Lee “Subword Parallelism with MAX-2” Hewlett Packard IEEE Micro, Aug. 1996 pp. 51-59.
A. Peleg et al. “MMX Technology Extension to the Intel Architecture” IEEE Micro Aug. 1996 pp. 42-50.
A. Peleg et al., “Intel MMX for Multimedia PCs” Communications of the ACMM Jauary 1997/vol. 40, No. 1 pp. 25-38.
Gschwind Michael Karl
Hofstee Harm Peter
Hopkins Martin Edward
International Business Machines - Corporation
Keusey, Tutunjian & & Bitetto, P.C.
Kim Kenneth S.
Percello Louis J.
LandOfFree
SIMD datapath coupled to scalar/vector/address/conditional... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with SIMD datapath coupled to scalar/vector/address/conditional..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and SIMD datapath coupled to scalar/vector/address/conditional... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3383427