Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2007-06-26
2007-06-26
Pan, Daniel (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S025000, C712S221000
Reexamination Certificate
active
10304341
ABSTRACT:
An operation method has processing for applying a same type of operation in parallel to N M-bit operands to obtain N M-bit operation results executed on a computer. Here, N is an integer equal to or greater than 2 and M is an integer equal to or greater than 1. The operation method includes: an operation step of applying the type of operation to an N*M-bit provisional operand that is formed by concatenating the N M-bit operands, to obtain one N*M-bit provisional operation result, and generating correction information based on an effect had, by applying the operation, on each M bits of the provisional operation result from a bit that neighbors the M bits; and a correction step of correcting the provisional operation result in M-bit units with use of the correction information, to obtain the N M-bit operation results.
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patent: 5847978 (1998-12-01), Ogura et al.
patent: 6282556 (2001-08-01), Chehrazi et al.
patent: 6704762 (2004-03-01), Inoue
patent: 3-268024 (1991-11-01), None
Matsushita Electric - Industrial Co., Ltd.
Pan Daniel
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