SIMD processor with scalar arithmetic logic units

Details SIMD processor with scalar arithmetic logic units SIMD processor with scalar arithmetic logic units

2006-12-05

2006-12-05

Fleming, Fritz (Department: 2181)

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

C712S002000, C712S009000

Reexamination Certificate

active

07146486

ABSTRACT:
A scalar processor that includes a plurality of scalar arithmetic logic units and a special function unit. Each scalar unit performs, in a different time interval, the same operation on a different data item, where each different time interval is one of a plurality of successive, adjacent time intervals. Each unit provides an output data item in the time interval in which the unit performs the operation and provides a processed data item in the last of the successive, adjacent time intervals. The special function unit provides a special function computation for the output data item of a selected one of the scalar units, in the time interval in which the selected scalar unit performs the operation, so as to avoid a conflict in use among the scalar units. A vector processing unit includes an input data buffer, the scalar processor, and an output orthogonal converter.

REFERENCES:
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patent: 4739474 (1988-04-01), Holsztynski
patent: 5179714 (1993-01-01), Graybill
patent: 5642444 (1997-06-01), Mostafavi
“Warp Architecture and Implementation” by Marco Annaratone, Emmanuel Arnould, Thomas Gross, H.T. Kung, Monica S. Lam, Onat Menzilcioglu, Ken Sarocky, and Jon A. Webb.

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