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Relay node communication interface transmitting update...

Electrical computers and digital processing systems: processing – Processing architecture – Distributed processing system
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Reliable branch predictions for real-time applications

Electrical computers and digital processing systems: processing – Processing control – Branching
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Reliable execution using compare and transfer instruction on...

Electrical computers and digital processing systems: processing – Processing control – Instruction modification based on condition
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Remote monitoring and control of equipment over computer...

Electrical computers and digital processing systems: processing – Processing architecture – Distributed processing system
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Removing local RAM size limitations when executing software...

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to generate an address of a microroutine
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Rename finish conflict detection and recovery

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Renaming apparatus and processor

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Renaming numeric and segment registers using common general regi

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Renaming registers to values produced by instructions...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Reorder buffer configured to allocate storage for...

Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
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Reorder buffer employed in a microprocessor to store instruction

Electrical computers and digital processing systems: processing – Instruction issuing – Simultaneous issuance of multiple instructions
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Reorder buffer employing last in line indication

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Reorder buffer having a future file for storing speculative inst

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Reorder buffer which forwards operands independent of storing de

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Reordering serial data in a system with parallel processing...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Repair of mis-predicted load values

Electrical computers and digital processing systems: processing – Instruction fetching
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Repeat block with zero cycle overhead nesting

Electrical computers and digital processing systems: processing – Processing control – Branching
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Repeat function for processing of repetitive instruction...

Electrical computers and digital processing systems: processing – Processing control – Branching
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Repeat instruction with interrupt

Electrical computers and digital processing systems: processing – Processing control – Branching
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Replacing displacement in control transfer instruction with enco

Electrical computers and digital processing systems: processing – Instruction decoding – Predecoding of instruction component
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