Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
Patent
1998-10-27
1999-07-13
Ellis, Richard L.
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Scoreboarding, reservation station, or aliasing
712 41, G06F 938
Patent
active
059220694
ABSTRACT:
A reorder buffer is provided which decouples allocation of storage space within the buffer for storing instructions from forwarding of the corresponding operands. When instructions are presented to the reorder buffer for storage and dependency checking, the reorder buffer allocates storage for the instructions and corresponding instruction results. If an unresolved dependency is detected, the instructions remain stored in the reorder buffer but operand forwarding is delayed until the unresolved dependency becomes resolved. Advantageously, the previously included extra storage and multiplexing prior to dependency checking may be eliminated. Additional clock cycle time may be available for performing dependency checking. Additionally, area formerly occupied by the extra storage is freed for other purposes.
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Advanced Micro Devices , Inc.
Ellis Richard L.
Kivlin B. Noel
Merkel Lawrence J.
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