Shared register architecture for a dual-instruction-set CPU to f
Sharing data in internal and memory representations with...
Sharing information to reduce redundancy in hybrid branch...
Shift and insert instruction for overwriting a subset of...
Sign generation bypass path to aligner for reducing signed...
Signal processing device and method for supplying a signal...
Signal processor capable of executing microprograms with differe
Signal processor for performing conditional operation
Signal processor having pipeline processing that supresses...
SIMD operation system capable of designating plural...
SIMD processor executing min/max instructions
SIMD processor executing min/max instructions
Simple branch prediction and misprediction recovery method
Simplified method to generate BTAGs in a decode unit of a...
Simultaneous speculative threading light mode
Single array banked branch target buffer
Single array banked branch target buffer
Single chip microcomputer having a dedicated address bus and...
Single cycle context switching by swapping a primary latch...
Single cycle context switching by swapping a primary latch...