Sign generation bypass path to aligner for reducing signed...

Details Sign generation bypass path to aligner for reducing signed... Sign generation bypass path to aligner for reducing signed...

2005-11-15

2005-11-15

Kim, Kenneth S. (Department: 2111)

Electrical computers and digital processing systems: processing

Processing control

Processing control for data transfer

C712S221000, C712S300000

Reexamination Certificate

active

06965985

ABSTRACT:
A method for reducing signed load latency in a microprocessor has been developed. The method includes transferring a part of data to an aligner via a bypass, and generating a sign bit from the part of the data. The sign bit is transferred to the aligner along the bypass, and the data is separately transferred to the aligner along a data path.

REFERENCES:
patent: 5638312 (1997-06-01), Simone
patent: 5909572 (1999-06-01), Thayer et al.
patent: 6311199 (2001-10-01), Tamura et al.
patent: 6557096 (2003-04-01), Ganapathy et al.
patent: 2002/0087839 (2002-07-01), Jarvis et al.

Affiliated with

Also associated with

Rating

Sign generation bypass path to aligner for reducing signed... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Sign generation bypass path to aligner for reducing signed..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sign generation bypass path to aligner for reducing signed... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3515436