Branch instruction prediction method

Details Branch instruction prediction method Branch instruction prediction method

1997-06-24

1999-08-24

Treat, William M.

Electrical computers and digital processing systems: processing

Processing control

Branching

G06F 938

Patent

active

059419857

ABSTRACT:
The outcome of a given branch instruction is predicted using early and late branch history addressing modes. In an early addressing process, a first subset of bits from a branch history register is used to first address a branch history table to obtain a plurality of candidate predictions. In a late addressing process, a second subset of bits from the branch history register is used to again address the branch history table to select one of the plurality of candidate predictions, the second subset of bits including additional branch history information loaded into the branch history register subsequent to the early addressing mode. In this way, more recent branch history information is used to predict the outcome of the given branch instruction.

REFERENCES:
patent: 5367703 (1994-11-01), Levitan
patent: 5423011 (1995-06-01), Blaner et al.
patent: 5434985 (1995-07-01), Emma et al.
patent: 5584001 (1996-12-01), Hoyt et al.
patent: 5623614 (1997-04-01), Van Dyke et al.
patent: 5742805 (1998-04-01), Kulkarni et al.
patent: 5758143 (1998-05-01), Levitan
patent: 5774710 (1998-06-01), Chung
patent: 5794028 (1998-08-01), Tran
patent: 5812838 (1998-09-01), Dhong et al.

Affiliated with

Also associated with

Rating

Branch instruction prediction method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Branch instruction prediction method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Branch instruction prediction method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-462646