Saving and restoring architectural state for processor cores
Scalable link stack control method with full support for...
Security on hardware loops
Selecting subroutine return mechanisms
Selecting subroutine return mechanisms
Selection of link and fall-through address using a bit in a...
Selective interrupt suppression
Selective postponement of branch target buffer (BTB) allocation
Selective signalling of later reserve location memory fault...
Self-priming loop execution for loop prolog instruction
Semiconductor device
Sequence control circuit
Setting breakpoint for postponed interrupt processing in...
Shared interrupt controller for a multi-threaded processor
Sharing information to reduce redundancy in hybrid branch...
Signal processor capable of executing microprograms with differe
Signal processor having pipeline processing that supresses...
Simple branch prediction and misprediction recovery method
Simplified method to generate BTAGs in a decode unit of a...
Single array banked branch target buffer