Boundary synchronization mechanism for a processor of a...

Branch instruction having different field lengths for...

Branch recovery mechanism to reduce processor front end stall ti

Broadcast invalidate scheme

Building a wavecache

Byte execution unit for carrying out byte instructions in a...

Cache consistent control of subsequent overlapping memory...

Can device featuring advanced can filtering and message...

Can microcontroller that permits concurrent access to...

Cascaded arithmetic pipeline data processor

Cascaded event detection modules for generating combined...

Cascaded microcomputer array and method

Cellular automaton processing microprocessor prefetching...

Cellular engine for a data processing system

Cellular engine for a data processing system

Center focused single instruction multiple data (SIMD) array...

Central processing unit and microcomputer having testing of circ

Central processing unit having instruction queue of 32-bit lengt

Central processing unit having instruction queue of 32-bit...

Central processing unit including APX and DSP cores which receiv