Cascaded arithmetic pipeline data processor

Details Cascaded arithmetic pipeline data processor Cascaded arithmetic pipeline data processor

1998-10-19

2000-11-28

Treat, William M.

Electrical computers and digital processing systems: processing

Processing architecture

Microprocessor or multichip or multimodule processor having...

348721, G06F 738

Patent

active

061548294

ABSTRACT:
Five processing units, namely one data memory, three arithmetic units, and one data memory, are connected together in a cascade arrangement so as to form a single arithmetic pipeline. Likewise, five control devices are connected together in a cascade arrangement and a control signal requesting that a series of data processing operations should start is sent to the first stage control device. Each control device starts to send a micro instruction to a corresponding processing unit upon detection of a processing start request bit in the received control signal and sends a signal which lags the control signal by a delay time equal to a number of cycles required to complete a processing operation of the processing unit, to the next stage control device. The first stage control device is provided with a loop counter operable to count the number of times processing is repeated and automatically generates a processing start request and a processing end request to the next stage control device.

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patent: 5777688 (1998-07-01), Miyake et al.
patent: 5943491 (1999-08-01), Sutherland et al.
patent: 6052706 (2000-04-01), Wheeler et al.

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