Cascaded microcomputer array and method

Details Cascaded microcomputer array and method Cascaded microcomputer array and method

2006-07-04

2006-07-04

Coleman, Eric (Department: 2183)

Electrical computers and digital processing systems: processing

Processing architecture

Microprocessor or multichip or multimodule processor having...

C712S203000

Reexamination Certificate

active

07073048

ABSTRACT:
A microcomputer array and method having a hyper-scalable, real-time monitoring and debug architecture in which several microcomputers are cascaded together into a single, more powerful unit. A cascaded instruction pipeline and related control circuitry allow a plurality of subprocessors or “proto-processors” to be cascaded with the instruction pipeline of a head processor or “nucleus processor” thereby creating an array of processors. The proto-processors may operate independently performing peripheral functions until a cascaded instruction takes priority and causes one or more proto-processors to perform the cascaded instruction and send the results to the nucleus processor. The processors may be microcomputers or Digital Signal Processors (DSPs).

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