Branch recovery mechanism to reduce processor front end stall ti

Details Branch recovery mechanism to reduce processor front end stall ti Branch recovery mechanism to reduce processor front end stall ti

1997-12-31

2000-02-15

An, Meng-Ai T.

Electrical computers and digital processing systems: processing

Processing architecture

Vector processor

712233, 712234, 712235, 712236, 712237, G06F 938

Patent

active

060264772

ABSTRACT:
An improved branch recovery mechanism includes an instruction fetch unit, an instruction decode stage, a branch prediction unit coupled to the decode stage for predicting whether the branch instruction will be taken, and an instruction pool for receiving and storing micro-ops. After a mispredicted branch is detected, micro-ops corresponding to a correct path are loaded into the instruction pool without waiting for the mispredicted branch instruction to be retired. By immediately loading the correct path into the instruction pool, Front End stall time can be reduced. Micro-ops in the instruction pool are distinguished based on path information for each micro-op stored in the instruction pool. The micro-ops corresponding to the mispredicted path are deleted as quickly as possible without committing their execution results to architectural state.

REFERENCES:
patent: 4974154 (1990-11-01), Matsuo
patent: 5542109 (1996-07-01), Blomgren et al.
patent: 5586278 (1996-12-01), Papworth
patent: 5729728 (1998-03-01), Colwell
patent: 5812839 (1998-09-01), Hoyt
Shanley, Tom "Pentium Pro Processor System Architecture," pp. 61-118, 1997.

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