Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2006-12-12
2006-12-12
Fleming, Fritz (Department: 2181)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S002000, C712S221000
Reexamination Certificate
active
07149877
ABSTRACT:
A disclosed byte execution unit receives byte instruction information and two operands, and performs an operation specified by the byte instruction information upon one or both of the operands, thereby producing a result. The byte instruction specifies either a count ones in bytes operation, an average bytes operation, an absolute differences of bytes operation, or a sum bytes into halfwords operation. In one embodiment, the byte execution unit includes multiple byte units. Each byte unit includes multiple population counters, two compressor units, adder input multiplexer logic, adder logic, and result multiplexer logic. A data processing system is described including a processor coupled to a memory system. The processor includes the byte execution unit. The memory system includes a byte instruction, wherein the byte instruction specifies either the count ones in bytes operation, the average bytes operation, the absolute differences of bytes operation, or the sum bytes into halfwords operation.
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Dhong Sang Hoo
Michael Brad William
Mueller Silvia Melitta
Oh Hwa-Joon
Tran Kevin D.
Fleming Fritz
Geib Benjamin
Gerhardt Diana R.
International Business Machines - Corporation
Tkacs Stephen R.
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