Electrical computers and digital processing systems: processing – Processing architecture – Microprocessor or multichip or multimodule processor having...
Reexamination Certificate
2000-08-01
2004-05-04
Vincent, David (Department: 2663)
Electrical computers and digital processing systems: processing
Processing architecture
Microprocessor or multichip or multimodule processor having...
C370S412000
Reexamination Certificate
active
06732254
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to the field of data communications, and more particularly, to the field of serial communications bus controllers and microcontrollers that incorporate the same.
CAN (Control Area Network) is an industry-standard, two-wire serial communications bus that is widely used in automotive and industrial control applications, as well as in medical devices, avionics, office automation equipment, consumer appliances, and many other products and applications. CAN controllers are currently available either as stand-alone devices adapted to interface with a microcontroller or as circuitry integrated into or modules embedded in a microcontroller chip. Since 1986, CAN users (software programmers) have developed numerous high-level CAN Application Layers (CALs) which extend the capabilities of the CAN while employing the CAN physical layer and the CAN frame format, and adhering to the CAN specification. CALs have heretofore been implemented primarily in software, with very little hardware CAL support. Consequently, CALs have heretofore required a great deal of host CPU intervention, thereby increasing the processing overhead and diminishing the performance of the host CPU.
Thus, there is a need in the art for a CAN hardware implementation of CAL functions normally implemented in software in order to offload these tasks from the host CPU to the CAN hardware, thereby enabling a great savings in host CPU processing resources and a commensurate improvement in host CPU performance. One of the most demanding and CPU resource-intensive CAL functions is message management, which entails the handling, storage, and processing of incoming CAL/CAN messages received over the CAN serial communications bus and/or outgoing CAL/CAN messages transmitted over the CAN serial communications bus. CAL protocols, such as DeviceNet, CANopen, and OSEK, deliver long messages distributed over many CAN frames, which methodology is sometimes referred to as “fragmented” or “segmented” messaging. The process of assembling such fragmented, multi-frame messages has heretofore required a great deal of host CPU intervention. In particular, CAL software running on the host CPU actively monitors and manages the buffering and processing of the message data, in order to facilitate the assembly of the message fragments or segments into complete messages.
Based on the above and foregoing, it can be appreciated that there presently exists a need in the art for a hardware implementation of CAL functions normally implemented in software in order to offload these tasks from the host CPU, thereby enabling a great savings in host CPU processing resources and a commensurate improvement in host CPU performance.
The assignee of the present invention has recently developed a new microcontroller product, designated “XA-C3”, that fulfills this need in the art. The XA-C3 is the newest member of the Philips XA (e
X
tended
A
rchitecture) family of high performance 16-bit single-chip microcontrollers. It is believed that the XA-C3 is the first chip that features hardware CAL support.
The XA-C3 is a CMOS 16-bit CAL/CAN 2.0B microcontroller that incorporates a number of different inventions, including the present invention. These inventions include novel techniques and hardware for filtering, buffering, handling, and processing CAL/CAN messages, including the automatic assembly of multi-frame fragmented messages with minimal CPU intervention, as well as for managing the storage and retrieval of the message data, and the memory resources utilized therefor.
The present invention relates to a CAN microcontroller that supports a plurality (e.g., 32) of message objects, each one of which is assigned a respective message buffer within an on-chip and/or off-chip portion of the overall data memory space of the CAN microcontroller. The location and size of each of the message buffers can be reconfigured by the user (programmer) by simple programming of memory-mapped registers provided for this purpose. The message buffers are used to store incoming (receive) messages and to stage outgoing (transmit) messages. With the XA-C3 microcontroller that constitutes a presently preferred implementation of the present invention, Direct Memory Access (DMA) is employed to enable the XA-C3 CAN module to directly access any of the 32 message buffers without interrupting the processor core. This message storage scheme provides a great deal of flexibility to the user, as the user is free to use as much or as little message storage area as an application requires, and is also free to position the message buffers wherever it is most convenient.
This message storage scheme is a key element of the unique “message management” capabilities of the XA-C3 CAN microcontroller, as this scheme enables the XA-C3 CAN/CAL module to concurrently assemble many (up to 32) incoming, fragmented messages of varying lengths, and, at the same time, stage multiple outgoing messages for tansmission. Since incoming message assembly is handled entirely in hardware, the processor is free to perform other tasks, typically until a complete message is received and ready for processing.
All CAN devices have the ability to perform receive acceptance filtering or screening. Acceptance filtering is typically accomplished by comparing information in the header portion of a received CAN message to be filtered or screened (and, in some cases, also the first and/or second byte in the data field of the received CAN message) to one or more pre-established values, sometimes called acceptance filters or screeners. Software running on the processor core can perform the acceptance filtering at the expense of performance, because software requires an ample amount of CPU resources and time to perform acceptance filtering. Therefore, hardware filtering is desired in order to reduce the burden or overhead processing load on the CPU (processor core). However, with the presently available technology, hardware filtering is far less flexible than software filtering, and greatly increases the required die area for implementation of the CAN device.
The presently available acceptance filtering techniques include the use of a match field and a mask field to create what is sometimes referred to as a “match and mask” filter. Each combination of available match and mask fields constitutes a separate filter or filter object. A basic CAN device will typically have one or two filters with full match and mask capabilities. A whole family of messages will typically be accepted. Software or hardware can be employed to actually perform the filtering. However, with the presently available technology, software must decide where to store each individual message. This type of filtering is generally the most flexible; however, it consumes the most CPU resources.
A full CAN device is one in which the hardware filters a message and matches it to one of a number of screeners to decide where to store the message. Each filter is linked to a message buffer. Upon a successful comparison of the incoming message header to one of the screeners, the message is stored in the message buffer associated with the matching screener. Generally, only “matching” and not “masking” is performed by each filter. However, there could be a “global mask” that is applied to all filters, or one filter could be designated to provide the “mask”.
Based on the above and foregoing, it can be appreciated that there presently exists a need in the art for a much more flexible and powerful technique for message acceptance filtering in a CAN device, e.g., a CAN microcontroller, that overcomes the above-discussed limitations and shortcomings of the presently available technology, particularly such a technique that does not explode the required die area to implement the CAN device, and which is performed in hardware, rather than software, to thereby minimize loading of the processor (CPU) core, and thereby dramatically improve system performance.
The present invention fulfills this need in the art. As will become appar
Birns Neil Edward
Fabbri Richard
Hao Hong Bin
Slivkoff William J.
Koninklijke Philips Electronics , N.V.
Vincent David
Waxler Aaron
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