Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2006-06-06
2006-06-06
Kim, Kenneth S. (Department: 2111)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C714S039000
Reexamination Certificate
active
07058790
ABSTRACT:
An eventpoint chaining apparatus for generalized event detection and action specification in a processing environment is described. In one aspect, the eventpoint chaining apparatus includes a first processor which has a programmable eventpoint module with an input trigger (InTrig) input. The first processing element detects an occurrence of a first processor event (p-event) and produces an OutTrigger (OT) signal. The eventpoint chaining apparatus also includes a second processor which has a programmable eventpoint module with an input trigger (InTrig) input which receives the OT signal from the first processing element. The second processing element detects an occurrence of a second p-event and produces, in response to the OT signal received from the first processing element and the detection of a second p-event, an eventpoint (EP) interrupt signal. The eventpoint chaining apparatus also includes a sequence processor interrupt control unit for receiving the EP interrupt signals indicating the occurrence of both the first and second p-events and causing a p-action in response to the occurrence of both the first and second p-events.
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Barry Edwin Franklin
Kurak, Jr. Charles W.
Marchand Patrick R.
Pechanek Gerald George
Kim Kenneth S.
Priest & Goldstein PLLC
PTS Corporation
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