Internal bus system for DFPS and units with two- or...
Internal bus system for DFPS and units with two- or...
Irregular network
Iteratively processing data segments by concurrently...
Line-plane broadcasting in a data communications network of...
Load and store unit for a vector processor
Load/store operation of memory misaligned vector data using...
Local and global register partitioning technique
Local control of multiple context processing elements with...
Local control of multiple context processing elements with...
Local stall control method and structure in a microprocessor
Locating and sampling of data in parallel processing systems
Logic integrated circuit, and recording medium readable by a...
Long instruction word processing with instruction extensions
Loop handling for single instruction multiple datapath...
Loosely-biased heterogeneous reconfigurable arrays
Machine for processing interrupted out-of-order instructions
Macroscalar processor architecture
Managing buffer storage in a parallel processing environment
Managing data forwarded between processors in a parallel...