Local and global register partitioning technique

Details Local and global register partitioning technique Local and global register partitioning technique

2006-09-19

2008-10-14

Treat, William M (Department: 2181)

Electrical computers and digital processing systems: processing

Processing architecture

Distributed processing system

C712S024000, C711S148000

Reexamination Certificate

active

07437534

ABSTRACT:
A Very Long Instruction Word (VLIW) processor having a plurality of functional units includes a multi-ported register file that is divided into a plurality of separate register file segments, each of the register file segments being associated to one of the plurality of functional units. The register file segments are partitioned into local registers and global registers. The global registers are read and written by all functional units. The local registers are read and written only by a functional unit associated with a particular register file segment. The local registers and global registers are addressed using register addresses in an address space that is separately defined for a register file segment/functional unit pair. The global registers are addressed within a selected global register range using the same register addresses for the plurality of register file segment/functional unit pairs. The local registers in a register file segment are addressed using register addresses in a local register range outside the global register range that are assigned within a single register file segment/functional unit pair. Register addresses in the local register range are the same for the plurality of register file segment/functional unit pairs and address registers locally within a register file segment/functional unit pair.

REFERENCES:
patent: 5301340 (1994-04-01), Cook
patent: 5655132 (1997-08-01), Watson
patent: 5732250 (1998-03-01), Bates et al.
patent: 6192384 (2001-02-01), Dally et al.
patent: 6219777 (2001-04-01), Inoue
Rotenberg et al., “Trace Processors”, Proceedings of the thirtieth Annual IEEE/ACM International Symposium on Microrarchitecture, Dec. 1-3, 1997, pp. 138-148.
Farkas et al., “The Multicluster Architecture: Reducing Cycle Time through Partitioning”, Proceedings of the thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, Dec. 1-3, 1997, pp. 149-159.
Llosa et al., “Non-Consistent Dual Register Files to Reduce Register Pressure”, Proceedings of the First IEEE Symposium on High-Performance Computer Architecture, Jan. 22-25, 1995, pp. 22-31.

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