Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2005-05-16
2008-12-02
Kim, Matt (Department: 2184)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S015000, C712S011000, C712S016000
Reexamination Certificate
active
07461234
ABSTRACT:
A heterogeneous array includes clusters of processing elements. The clusters include a combination of ALUs and multiplexers linked by direct connections and various general-purpose routing networks. The multiplexers are controlled by the ALUs in the same cluster, or alternatively by ALUs in other clusters, via a special purpose routing network. Components of applications configured onto the array are selectively implemented in either multiplexers or ALUs, as determined by the relative efficiency of implementing the component in one or the other type of processing element, and by the relative availability of the processing element types. Multiplexer control signals are generated from combinations of ALU status signals, and optionally routed to control multiplexers in different clusters.
REFERENCES:
patent: 4811214 (1989-03-01), Nosenchuck et al.
patent: 5038386 (1991-08-01), Li
patent: 5442577 (1995-08-01), Cohen
patent: 5448496 (1995-09-01), Butts et al.
patent: 5715186 (1998-02-01), Curtet
patent: 5742180 (1998-04-01), DeHon et al.
patent: 5829262 (1998-11-01), Urata et al.
patent: 5988881 (1999-11-01), Sutherland
patent: 6023573 (2000-02-01), Bai et al.
patent: 6052773 (2000-04-01), DeHon et al.
patent: 6088526 (2000-07-01), Ting et al.
patent: 6092174 (2000-07-01), Roussakov
patent: 6145072 (2000-11-01), Shams et al.
patent: 6405299 (2002-06-01), Vorbach et al.
patent: 6469540 (2002-10-01), Nakaya
patent: 6526498 (2003-02-01), Mirsky et al.
patent: 6609189 (2003-08-01), Kuszmaul et al.
patent: 6684318 (2004-01-01), DeHon et al.
patent: 6738891 (2004-05-01), Fujii et al.
patent: 6769056 (2004-07-01), Barry et al.
patent: 6781408 (2004-08-01), Langhammer
patent: 6859869 (2005-02-01), Vorbach
patent: 7272691 (2007-09-01), Stewart et al.
patent: 2002/0138716 (2002-09-01), Master
patent: 2003/0135710 (2003-07-01), Farwell et al.
patent: 2004/0001445 (2004-01-01), Stansfield
patent: 2004/0027155 (2004-02-01), Schlansker et al.
patent: 2004/0208171 (2004-10-01), Ovadia et al.
patent: 2005/0063373 (2005-03-01), DeHon et al.
patent: WO 00/69073 (2000-11-01), None
patent: WO 2004/075403 (2004-09-01), None
Alan Marshall et al. A Reconfigurable Arithmetic Array for Multimedia Application, Proceedings of the 1999 ACM/SIGDA on FPGA.
Kai Hwang, Advanced Computer Architecture, McGraw Hill, 1993.
Bursky, D, “PFGA Combines Multiple Serial Interfaces and Logic” Electronic Design, Penton Publishing, Cleveland, Ohio vol. 28, No. 20, Oct. 2, 2000, pp. 74-76, 78.
“Virtex-II 1.5V Field-Programmable Gate Arrays”, Virtex-II Platform FPGA Handbook, Xilinx Inc, v1.0, Dec. 6, 2000, p. 47.
Anthony Stansfield and Ian Page, “The Design of a New FPGA Architecture”, 1995, Proceedings of FPL 1995 Conference, pp. 1-14.
Marshall Alan D
Olgiati Andrea
Ray Nicholas John Charles
Stansfield Anthony I.
Kim Matt
Orrick Herrington & Sutcliffe LLP
Panasonic Corporation
Tseng Cheng-Yuan
LandOfFree
Loosely-biased heterogeneous reconfigurable arrays does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Loosely-biased heterogeneous reconfigurable arrays, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Loosely-biased heterogeneous reconfigurable arrays will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4047925