Internal bus system for DFPS and units with two- or...

Details Internal bus system for DFPS and units with two- or... Internal bus system for DFPS and units with two- or...

2006-03-07

2006-03-07

Vo, Tim (Department: 2112)

Electrical computers and digital processing systems: processing

Processing architecture

Array processor

C703S023000, C326S039000

Reexamination Certificate

active

07010667

ABSTRACT:
An internal bus system for DFPs and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity. The bus system can transmit data between a plurality of function blocks, where multiple data packets can be on the bus at the same time. The bus system automatically recognizes the correct connection for various types of data or data transmitters and sets it up.

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