Load/store operation of memory misaligned vector data using...

Details Load/store operation of memory misaligned vector data using... Load/store operation of memory misaligned vector data using...

2007-05-15

2007-05-15

Kim, Kenneth S. (Department: 2111)

Electrical computers and digital processing systems: processing

Processing architecture

Vector processor

C712S004000, C712S225000

Reexamination Certificate

active

11067106

ABSTRACT:
A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one aspect, the processor supports three possible instruction sizes while maintaining the simplicity of programming and allowing efficient physical implementation. Most of the application code can be encoded using two sets of narrow size instructions to achieve high code density. Adding a third (and larger, i.e. VLIW) instruction size allows the architecture to encode multiple operations per instruction for the performance critical section of the code. Further, each operation of the VLIW format instruction can optionally be a SIMD operation that operates upon vector data. A scheme for the optimal utilization (highest achievable performance for the given amount of hardware) of multiply-accumulate (MAC) hardware is also provided.

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