Machine for processing interrupted out-of-order instructions

Details Machine for processing interrupted out-of-order instructions Machine for processing interrupted out-of-order instructions

1993-03-09

1999-10-26

Kim, Kenneth S.

Electrical computers and digital processing systems: processing

Processing architecture

Superscalar

712215, 713502, 710267, G06F 938

Patent

active

059745223

ABSTRACT:
A processor having multiple functional units. The processor is capable of executing multiple instructions concurrently. An instruction issuing unit is connected to a mechanism for handling an interrupt of the processor. The interrupt handler has an instruction window (IW), which includes a vector element number (VEN) field that indicates the uncompleted elements to be executed. Upon termination of the interrupt, normal processing of the instruction issuing unit continues.

REFERENCES:
patent: 4745547 (1988-05-01), Buchholz et al.
patent: 4780820 (1988-10-01), Sowa
patent: 4782441 (1988-11-01), Inagami et al.
patent: 4807115 (1989-02-01), Torng
R.D. Acosta, "An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors" IEEE Transactions on Computers vol. C-25, No. 9, Sep. 1986.

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