Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2007-08-22
2010-11-23
Petranek, Jacob (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S011000, C712S012000
Reexamination Certificate
active
07840779
ABSTRACT:
Methods, apparatus, and products are disclosed for line-plane broadcasting in a data communications network of a parallel computer, the parallel computer comprising a plurality of compute nodes connected together through the network, the network optimized for point to point data communications and characterized by at least a first dimension, a second dimension, and a third dimension, that include: initiating, by a broadcasting compute node, a broadcast operation, including sending a message to all of the compute nodes along an axis of the first dimension for the network; sending, by each compute node along the axis of the first dimension, the message to all of the compute nodes along an axis of the second dimension for the network; and sending, by each compute node along the axis of the second dimension, the message to all of the compute nodes along an axis of the third dimension for the network.
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Archer Charles J.
Berg Jeremy E.
Blocksome Michael A.
Smith Brian E.
Biggers & Ohanian LLP
International Business Machines - Corporation
Petranek Jacob
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