Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
1998-08-28
2002-06-11
Iqbal, Nadeem (Department: 2181)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S010000, C712S013000, C712S014000, C712S016000
Reexamination Certificate
active
06405299
ABSTRACT:
BACKGROUND INFORMATION
FPGAs and DPGAs, and similar systems with two- or multi-dimensional programmable cell architectures, have internal bus systems which either have a global connection to all or most of the logic cells or have a local next-neighbor connection. Both types have in common the fact that they involve connections between two or more logic cells. In addition, always exactly one signal can use the bus, unless a multiplexer architecture is configured together with a control into a plurality of logic cells.
According to German Patent No. DE 44 16 881, the bus systems described above already exist in DFP-based systems. In addition, there is the possibility of separating a bus system, thus resulting in several sub-buses that can be used separately.
In German Application No. DE 196 54 595.1-53, an I/O bus system is described which combines a plurality of bus systems within the unit, where a unit may be an FPGA, a DPGA, a DFP, etc., and leads out of the unit. Memory modules or peripheral devices or other units of the generic type mentioned above can be triggered in this way. There is only one address register or address counter to generate the external addresses.
Conventional bus systems are not suitable for transmitting large volumes of data in the form of signals grouped by bytes or otherwise. Especially when the units are used for computation of algorithms, it is necessary for a plurality of data (packets) to be transmitted simultaneously between the individual configured function areas of a unit. In the usual technology, a direct point-to-point connection must be set up for each data path, which is the connection (the bus) between two (or more) function blocks that receive the same data, and which then regulates the data traffic between these function blocks exclusively. There can be only one data packet on the bus at a time. The interconnection complexity is very high. The transmission rate of today's internal buses is limited by the maximum bus size and the signal propagation time on the bus. With the I/O bus described in German Application No. DE 196 54 595.1-53, only one type of bus connection can be set up per I/O cell, namely exclusively that programmed in the address register. There is no possibility of responding to different types of data or data transmitters and connecting them to different external units.
SUMMARY OF THE INVENTION
An object of the present invention is to create a bus system that can transmit data between a plurality of function blocks, where multiple data packets can be on the bus at the same time. The bus system automatically recognizes the correct connection for various types of data or data transmitters and sets it up.
REFERENCES:
patent: 4706216 (1987-11-01), Carter
patent: 4739474 (1988-04-01), Holsztynski et al.
patent: 4761755 (1988-08-01), Ardini et al.
patent: 4811214 (1989-03-01), Nosenchuck et al.
patent: 4870302 (1989-09-01), Freeman
patent: 4901268 (1990-02-01), Judd
patent: 4967340 (1990-10-01), Dawes
patent: 5014193 (1991-05-01), Garner et al.
patent: 5015884 (1991-05-01), Agrawal et al.
patent: 5021947 (1991-06-01), Campbell et al.
patent: 5023775 (1991-06-01), Poret
patent: 5081375 (1992-01-01), Pickett et al.
patent: 5109503 (1992-04-01), Cruichkshank et al.
patent: 5123109 (1992-06-01), Hillis
patent: 5125801 (1992-06-01), Nabity et al.
patent: 5128559 (1992-07-01), Steele
patent: 5142469 (1992-08-01), Weisenborn
patent: 5204935 (1993-04-01), Mihara et al.
patent: 5208491 (1993-05-01), Ebeling et al.
patent: 5226122 (1993-07-01), Thayer et al.
patent: RE34363 (1993-08-01), Freeman
patent: 5233539 (1993-08-01), Agrawal et al.
patent: 5247689 (1993-09-01), Ewert
patent: 5287472 (1994-02-01), Horst
patent: 5301344 (1994-04-01), Kolchinsky
patent: 5303172 (1994-04-01), Magar et al.
patent: 5336950 (1994-08-01), Popli et al.
patent: 5361373 (1994-11-01), Gilson
patent: 5418952 (1995-05-01), Morley et al.
patent: 5421019 (1995-05-01), Holsztynski et al.
patent: 5422823 (1995-06-01), Agrawal et al.
patent: 5426378 (1995-06-01), Ong
patent: 5430687 (1995-07-01), Hung et al.
patent: 5440245 (1995-08-01), Galbraith et al.
patent: 5442790 (1995-08-01), Nosenchuck
patent: 5444394 (1995-08-01), Watson et al.
patent: 5448186 (1995-09-01), Kawata
patent: 5455525 (1995-10-01), Ho et al.
patent: 5457644 (1995-10-01), McCollum
patent: 5473266 (1995-12-01), Ahanin et al.
patent: 5473267 (1995-12-01), Stansfield
patent: 5475583 (1995-12-01), Bock et al.
patent: 5475803 (1995-12-01), Stearns et al.
patent: 5483620 (1996-01-01), Pechanek et al.
patent: 5485103 (1996-01-01), Pedersen et al.
patent: 5485104 (1996-01-01), Agrawal et al.
patent: 5489857 (1996-02-01), Agrawal et al.
patent: 5491353 (1996-02-01), Kean
patent: 5493239 (1996-02-01), Zlotnick
patent: 5497498 (1996-03-01), Taylor
patent: 5506998 (1996-04-01), Kato et al.
patent: 5510730 (1996-04-01), El Gamal et al.
patent: 5511173 (1996-04-01), Yamaura et al.
patent: 5513366 (1996-04-01), Agrawal et al.
patent: 5521837 (1996-05-01), Frankle et al.
patent: 5522083 (1996-05-01), Gove et al.
patent: 5532693 (1996-07-01), Winters et al.
patent: 5532957 (1996-07-01), Malhi
patent: 5535406 (1996-07-01), Kolchinsky
patent: 5537057 (1996-07-01), Leong et al.
patent: 5537601 (1996-07-01), Kimura et al.
patent: 5541530 (1996-07-01), Cliff et al.
patent: 5544336 (1996-08-01), Kato et al.
patent: 5548773 (1996-08-01), Kemney et al.
patent: 5555434 (1996-09-01), Carlstedt
patent: 5559450 (1996-09-01), Ngai et al.
patent: 5561738 (1996-10-01), Kinerk et al.
patent: 5570040 (1996-10-01), Lytle et al.
patent: 5583450 (1996-12-01), Trimberger et al.
patent: 5586044 (1996-12-01), Agrawal et al.
patent: 5587921 (1996-12-01), Agrawal et al.
patent: 5588152 (1996-12-01), Dapp et al.
patent: 5590345 (1996-12-01), Barker et al.
patent: 5617547 (1997-04-01), Feeney et al.
patent: 5717943 (1998-02-01), Barker et al.
patent: 5838165 (1998-11-01), Chatter
patent: 5892961 (1999-04-01), Trimberger
patent: 5936424 (1999-08-01), Young et al.
patent: 5943242 (1999-08-01), Vorbach et al.
patent: 6014509 (2000-01-01), Furtek et al.
patent: 6054873 (2000-04-01), Laramie
patent: 4416881 (1994-11-01), None
patent: 0 221 360 (1987-05-01), None
patent: 028327 (1991-05-01), None
patent: 748 051 (1991-12-01), None
patent: 0539595 (1993-05-01), None
patent: 0 678 985 (1995-10-01), None
patent: 0 726 532 (1996-08-01), None
patent: 735 685 (1996-10-01), None
patent: WO90/11648 (1990-10-01), None
patent: 94/08399 (1994-04-01), None
Villasenor, John, et al., “Configurable Computing.”Scientific American, vol. 276, No. 6, Jun. 1997, pp. 66-71.
Villasenor, John, et al., “Configurable Computing Solutions for Automatic Target Recognition,”IEEE, 1996 pp. 70-79.
Tau, Edward, et al., “A First Generation DPGA Implementation,”FPD'95, pp. 138-143.
Athanas, Peter, et al., “IEEE Symposium of FPGAs For Custom Computing Machines,” IEEE Computer Society Press, Apr. 19-21, 1995, pp. i-vii, 1-222.
Bittner, Ray, A., Jr., “Wormhole Run-Time Reconfiguration: Conceptualization and VLSI Design of a High Performance system,”Dissertation, Jan. 23, 1997, pp. u-xx, 1-415.
Myers, G., Advances in Computer Architecture, Wiley-Interscience Publication, 2nd ed., John Wiley & Sons, Inc. pp. 463-494, 1978.
M. Saleeba, “A Self-Contained Dynamically Reconfigurable Processor Architecture”, Sixteenth Australian Computer Conference, ASCS-16, QLD, Australia, Feb., 1993.
M. Morris Mano, “Digital Design,” by Prentice Hall, Inc., Englewood Cliffs, New Jersey 07632, 1984, pp. 119-125, 154-161.
Maxfield, C. “Logic that Mutates While-U-Wait” EDN (Bur. Ed) (USA), EDN (European Edition), Nov. 7, 1996, Cahners Publishing, USA.
Münch Robert
Vorbach Martin
Iqbal Nadeem
Kenyon & Kenyon
PACT GmbH
Vo Tim
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