Processor instruction control mechanism capable of decoding regi

Processor system having accelerator of Java-type of...

Processor which overrides default operand size for implicit...

Processor which overrides default operand size for implicit...

Processor with different width functional units ignoring...

Processor with enhanced instruction set

Processor with instruction qualifiers to control MMU operation

Processor, compiling apparatus, and compile program recorded...

Processors operable to allow flexible instruction alignment

Program execution method and program execution device

Reconfigurable CPU with second FSM control unit executing...

Reducing the length of lower level instructions by splitting...

Register file access

Register move instruction for section select of source operand

Register move instruction for section select of source operand

Register set extension for compressed instruction set

Removing local RAM size limitations when executing software...

Replacing displacement in control transfer instruction with enco

Secondary trace build from a cache of translations in a...

Secure execution of program instructions provided by network...