Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...
Reexamination Certificate
2001-09-12
2008-10-07
Nguyen, Van H (Department: 2194)
Electrical computers and digital processing systems: processing
Instruction decoding
Decoding instruction to accommodate plural instruction...
C717S118000, C717S136000, C717S139000
Reexamination Certificate
active
07434030
ABSTRACT:
In a processor system comprising of a processor having an instruction decoder22, a general register61composed of a plurality of register areas and at least one ALU60, and a Java accelerator30for converting a Java bytecode sequence to a native instruction sequence for the processor and supplying the native instruction sequence to the instruction decoder. The Java accelerator30is composed of a bytecode translator40for converting the Java bytecode sequence to the native instruction sequence for the processor and a register status control unit50for mapping a Java operand stack to any of the register areas of the general register and detecting a bytecode redundant for the processor. When a redundant bytecode is detected by the register status control unit50, the supply of the native instruction from the bytecode translator40to the instruction decoder22is inhibited.
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Arakawa Fumio
Irie Naohiko
A. Marquez, Esq. Juan Carlos
Fisher Esq. Stanley P.
Nguyen Van H
Reed Smith LLP
Renesas Technology Corp.
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