Processors operable to allow flexible instruction alignment

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate variable length...

Reexamination Certificate

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Reexamination Certificate

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08006071

ABSTRACT:
Methods and apparatus are provided for optimizing a processor core. Common processor subcircuitry is used to perform calculations for various types of instructions, including branch and non-branch instructions. Increasing the commonality of calculations across different instruction types allows branch instructions to jump to byte aligned memory address even if supported instructions are multi-byte or word aligned.

REFERENCES:
patent: 5187791 (1993-02-01), Baum
patent: 5420992 (1995-05-01), Killian et al.
patent: 6219833 (2001-04-01), Solomon et al.
patent: 6463520 (2002-10-01), Otani et al.
patent: 6658550 (2003-12-01), Martin et al.
patent: 6772326 (2004-08-01), Chauvel et al.
patent: 6968547 (2005-11-01), Cantrill
patent: 7178013 (2007-02-01), Batcher
patent: RE039519 (2007-03-01), Bak et al.
patent: 2002/0049964 (2002-04-01), Takayama et al.
patent: 2002/0053711 (2002-05-01), Chau et al.
patent: 2002/0073407 (2002-06-01), Takayama et al.
patent: 2002/0078323 (2002-06-01), Takayama et al.
patent: 2003/0204705 (2003-10-01), Oldfield et al.
patent: 2004/0049656 (2004-03-01), Watanabe
patent: 2005/0223198 (2005-10-01), Ball
patent: 1690951 (2005-11-01), None
patent: 101387951 (2009-03-01), None
patent: 0897147 (1999-02-01), None
patent: 0953898 (1999-11-01), None
patent: 1582974 (2005-10-01), None
Wolf and Tauber, “Silicon processing for the VLSI Era”, vol. 1, p. 520, Lattice Press (1986).
Intel, Inc., “IA-32(R) Architecture Software Developer's Manual”, 2002, vols. 1-2.
Intel, Inc., “P6 Family of Processors Hardware Developer's Manual”, Sep. 1998.
“Data Alignment When Migrating to 64-bit Intel Architecture,” Intel.
Wittig et al.; “OneChip: An FPGA Processor with Reconfigurable Logic”; 1996; IEEE.
Linley Gwennap, “Intel Discloses New IA-64 Features Rotating Registers Reduce Code Expansion: Merced Touted for Big Servers” Microdesign Resources, Mar. 8, 1999, Microprocessor Report.
Lars T. Hansen, “Larceny Note #6: Larceny on the SPARC” retrieved from www.ccs.neu.edu/home/will/larceny
otes
otes6-sparc.html, May 5, 1998.
MIPS Instruction Reference, retrieved from www.mrc.uidaho.edu/people/jff/digital/MIPSir.html. updated Sep. 10, 1998.
Nikolova et al., “A Compression/Decompression Scheme for Embedded Systems Code”, Electronic Systems and Control Division Research 2003, pp. 36-38.
Office Action dated Feb. 6, 2008; U.S. Appl. No. 11/076,307.
European patent application No. 05251951.9, European Search Report mailed Feb. 2, 2008.
Gwennap, Linley “Intel Discloses New IA-64 Features, Rotating Registers Reduce Code Expansion; Merced Touted for Big Servers”, Microdesign Resources—Microprocessor Report, Mar. 8, 1999, 4 pages.
“Altera 20. Instruction Set Reference”, Altera Corporation, Dec. 2004, 102 pages.
Hennessy, John et al., “Computer Architecture—A Quantitative Approach”, Third Edition, downloaded from http://books.elsevier.com on Mar. 13, 2006, 26 pages.
U.S. Appl. No. 11/076,307, Office Action mailed Mar. 8, 2007.
U.S. Appl. No. 11/076,307, Office Action mailed Aug. 21, 2007.
Wolf, Stanley et al. “Silicon Processing for the VLSI Era, vol. 1: Process Technology”, 1986, Lattice Press, 2 pages.
Altera Corporation, Nios II Processor Reference Handbook, Chapter 20 Instruction Set Reference, pp. 20-1 thru 20-102, Dec. 2004, San Jose, California.
Final Office Action dated Jul. 30, 2008 in U.S. Appl. No. 11/076,307.
European Office Action dated Aug. 5, 2009 in Application No. 05251951.9.
Chinese Office Action dated Nov. 2, 2007 in Application No. 200510076224.1.
US Office Action dated Dec. 18, 2008 from U.S. Appl. No. 11/076,307.
US Final Office Action dated Jun. 8, 2009 from U.S. Appl. No. 11/076,307.
US Non-final Office Action dated Dec. 15, 2009 from U.S. Appl. No. 11/076,307.
US Final Office Action dated Apr. 30, 2010 from U.S. Appl. No. 11/076,307.
Chinese Office Action dated Jul. 13, 2010 from Application No. 200810173125.9.
English Translation of Claims in Chinese Publication No. 1690951.
English Translation of Claims in Chinese Publication No. 101387951.

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