Speculative execution control with programmable indicator...

Speculative execution of a load instruction by associating...

Speculative generation at address generation stage of...

Speculative instructions exection in VLIW processors

Speculative issue of instructions under a load miss shadow

Speculative renaming of data-processor registers

Split data-flow scheduling mechanism

Stall control

Stall-free pipelined cache for statically scheduled and...

Stick and spoke replay with selectable delays

Stitching parcels

Stopping replay tornadoes

Store load forward predictor training

Store load forward predictor untraining

Store queue architecture for a processor that supports...

Store to load forward predictor training using delta tag

Storing results of producer instructions to facilitate...

Streaming vector processor with reconfigurable...

Substitute register for use in a high speed data processor

Superscalar microprocessor employing a future file for storing r