Stall control

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble

Reexamination Certificate

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Reexamination Certificate

active

06993641

ABSTRACT:
Processors comprising a plurality of pipelines are disclosed, each pipeline having a plurality of pipeline stages (142, 146) for executing an instruction on successive clock cycles. The processors include distributed stall control circuitry (148, 150, 152, 154) which allow an instruction in one pipeline to become temporarily out of step with an instruction in another pipeline. This may allow time for a global signal, such as a global stall signal, to be distributed.

REFERENCES:
patent: 5860000 (1999-01-01), Biswas et al.
patent: 6044456 (2000-03-01), Murty et al.
patent: 6279100 (2001-08-01), Tremblay et al.
patent: 6477638 (2002-11-01), Gearty et al.
patent: 6587940 (2003-07-01), Soltis et al.
patent: 2 348 526 (2000-10-01), None
patent: 00/33183 (2000-06-01), None

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