Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
Reexamination Certificate
2006-01-31
2006-01-31
Treat, William M. (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Reducing an impact of a stall or pipeline bubble
Reexamination Certificate
active
06993641
ABSTRACT:
Processors comprising a plurality of pipelines are disclosed, each pipeline having a plurality of pipeline stages (142, 146) for executing an instruction on successive clock cycles. The processors include distributed stall control circuitry (148, 150, 152, 154) which allow an instruction in one pipeline to become temporarily out of step with an instruction in another pipeline. This may allow time for a global signal, such as a global stall signal, to be distributed.
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Topham Nigel Peter
Wong Kar-Lik Kasim
Greer Burns & Crain Ltd.
PTS Corporation
Treat William M.
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