Stall-free pipelined cache for statically scheduled and...

Details Stall-free pipelined cache for statically scheduled and... Stall-free pipelined cache for statically scheduled and...

2007-08-16

2011-11-22

Li, Aimee (Department: 2183)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Reducing an impact of a stall or pipeline bubble

Reexamination Certificate

active

08065505

ABSTRACT:
This invention provides flexible load latency to pipeline cache misses. A memory controller selects the output of one of a set of cascades inserted execute stages. This selection may be controlled by a latency field in a load instruction or by a latency specification of a prior instruction. This invention is useful in the great majority of cases where the code can tolerate incremental increases in load latency for a reduction in cache miss penalty.

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