Store queue architecture for a processor that supports...

Details Store queue architecture for a processor that supports... Store queue architecture for a processor that supports...

2007-07-09

2010-12-07

Li, Aimee J (Department: 2183)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

C712S218000, C712S219000

Reexamination Certificate

active

07849290

ABSTRACT:
Embodiments of the present invention provide a system that buffers stores on a processor that supports speculative execution. The system starts by buffering a store into an entry in the store queue during a speculative execution mode. If an entry for the store does not already exist in the store queue, the system writes the store into an available entry in the store queue and updates a byte mask for the entry. Otherwise, if an entry for the store already exists in the store queue, the system merges the store into the existing entry in the store queue and updates the byte mask for the entry to include information about the newly merged store. The system then forwards the data from the store queue to subsequent dependent loads.

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