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Reorder buffer having a future file for storing speculative inst

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Reorder buffer which forwards operands independent of storing de

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Reordering serial data in a system with parallel processing...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Reservation stations to increase instruction level parallelism

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Resolving dependencies among concurrently dispatched...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Resource management using multiply pendent registers

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Result forwarding of either input operand to same operand...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Retaining flag value associated with dead result data in...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Retiring early-completion instructions to improve computer...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Retiring early-completion instructions to improve computer...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
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Retiring instructions that meet the early-retirement...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Run-time parallelization of loops in computer programs by...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Runtime critical load/data ordering

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Scan chains for out-of-order load/store execution control

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Scheduling instructions in a cascaded delayed execution...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Reducing an impact of a stall or pipeline bubble
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Scheduling instructions with different latencies

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Scheduling operations using a dependency matrix

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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Scoreboard mechanism for serialized string operations...

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
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Secondary reorder buffer microprocessor

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
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Segmented pipeline flushing for mispredicted branches

Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or...
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