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Interface for high speed memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
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Interface for high speed memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Patent

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Interface for multi-processor

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate

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Interface protocol for a disk drive, SRAM and DRAM

Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or...
Reexamination Certificate

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Interface queue with bypassing capability for main storage unit

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Interface systems and methods for accessing stored data

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Interfaces for flexible storage management

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Interfacing an L2 cache to a single bus having alternative proto

Electrical computers and digital processing systems: memory – Storage accessing and control
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Interfacing of functional modules in an on-chip system

Electrical computers and digital processing systems: memory – Storage accessing and control
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Intergrated circuit and a method of cache remapping

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Interlaced memory device with random or sequential access

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Interleave address generation device and interleave address...

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Interleave memory control apparatus and method

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Interleave pre-checking in front of shared caches with...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Interleave read address generator

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Interleaved burst XOR using a single memory pointer

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Interleaved data path and output management architecture for...

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Interleaved memory device for burst type access in...

Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
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Interleaved n-way set-associative external cache

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Interleaver for iterative decoder

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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