Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2001-11-02
2003-11-04
Elmore, Reba I. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S147000, C711S165000
Reexamination Certificate
active
06643749
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a technology for interfacing processors which is suitable for a multi-processor system.
A multi-processor is effective in a system in which a single processor is severely lacking in processing ability, e.g., in a large-scale digital signal processing system. In particular, a tightly coupled multi-processor is well known. The tightly coupled multi-processor in which a single address space is shared by a plurality of processors is also termed a shared memory multi-processor (See TMS320C5x User's Guide, Chapter 6.4, Texas Instruments Inc., Jan. 1993).
An interface for the shared memory multiprocessor requires arbitration logic for arbitrating between memory access requests issued from the individual processors. Even if the individual processors constituting the multi-processor are improved in performance, the problem is encountered that an inefficient interface inhibits an improvement in the performance of the entire system.
In a multi-processor using a system in which processed data is passed between the individual processors with the flow of digital signal processing, it is desirable to directly connect the individual processors under a constraint on the area of a printed circuit board.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an interface for a multi-processor which enables efficient data transmission between processors.
To attain the object, the present invention has accomplished efficient data transmission between the processors by using the technology of message passing including the passing of address information for an internal data memory or a local memory. A memory access is in the form of block transfer performed by, e.g., specifying a start address and an end address.
Specifically, an interface for a multi-processor according to the present invention is an interface provided for each of a plurality of processors each having an internal data memory and connected to each other to constitute a multi-processor, the interface comprising: a data terminal for transmitting and receiving address information and data to be transferred; a mode terminal for transmitting and receiving a mode signal indicative of whether a signal at the data terminal represents the address information or the data to be transmitted; a read/write terminal for transmitting and receiving a read/write signal indicative of a timing for each of the signal at the data terminal and a signal at the mode terminal; an input buffer and an output buffer each connected to the data terminal; a data memory pointer connected to the internal data memory; and a control circuit connected to the mode terminal and to the read/write terminal. For data transmission, the control circuit performs a control operation of: directing the data memory pointer to generate a read address to be given to the internal data memory based on address information for the internal data memory of an objective processor out of the plurality of processors, the address information being held in the input buffer, thereby reading data from the internal data memory, and directing the output buffer to hold the data that has been read; transmitting, in conjunction with the mode signal and in synchronization with the read/write signal, address information for the internal data memory of a cooperative processor out of the plurality of processors which information is held in the output buffer to the cooperative processor via the data terminal; and transmitting, in conjunction with the mode signal and in synchronization with the read/write signal, the data held in the output buffer to the cooperative processor via the data terminal. For data reception, the control circuit performs a control operation of: receiving, in conjunction with the mode signal and in synchronization with the read/write signal, address information transmitted from the cooperative processor via the data terminal and directing the input buffer to hold the address information that has been received; receiving, in conjunction with the mode signal and in synchronization with the read/write signal, data transmitted from the cooperative processor via the data terminal and directing the input buffer to hold the data that has been received; and directing the data memory pointer to generate, based on the address information held in the input buffer, a write address to be given to the internal data memory and thereby writing the data held in the input buffer into the internal data memory.
The present invention not only enables efficient data transfer between the processors but also improves the efficiency with which the multi-processor system is mounted on a printed circuit board by directly connecting the processors.
REFERENCES:
patent: 5644749 (1997-07-01), Obayashi
patent: 6212620 (2001-04-01), Kawasaki et al.
patent: 2002/0018394 (2002-02-01), Takahashi
patent: 0 345 738 (1989-12-01), None
patent: 0 502 214 (1992-09-01), None
patent: 5-307652 (1993-11-01), None
TMS320C5xUser's Guide, Chapter 6.4, Texas Instruments Inc., Jan. 1993.
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