Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1997-10-02
2001-11-20
Yoo, Do Hyun (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S217000
Reexamination Certificate
active
06321311
ABSTRACT:
CLAIM OF PRIORITY
This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C §119 from an application entitled
Interleave Read Address Generator
earlier filed in the Korean Industrial Property Office on Oct. 2, 1996, and there duly assigned Serial No. 96-43731 by that Office.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an interleaver for use in a CDMA (Code division Multiple Access) PCS (Personal Communications Services) mobile station, and more particularly to an interleave read address generator for generating an interleave read address for reading out data written in an interleave memory.
2. Description of the Related Art
In accordance with Standard SP-3384 for a CDMA PCS mobile station, it is specified that a CDMA PCS mobile station should perform an interleaving in order to prevent a burst error of a reverse channel. The interleaving is achieved by successively writing transmission data into an interleave memory and then successively reading out the data from the interleave memory.
A prior art interleaver necessarily includes an expensive ROM into which the interleave read address is written, thus increasing the cost of manufacturing the interleaver. Typically, in accordance with the above stated Standard SP-3384, the interleaver has a variable data rate. In other words, Standard SP-3384 specifies a data rate of 9600 bps and 14400 bps, a data rate of 4800 bps and 7200 bps, a data rate of 2400 bps and 3600 bps, and a data rate of 1200 bps and 1800 bps. The interleaver should perform the interleaving differently with respect to the respective data rates. Accordingly, a CDMA system with the variable data rate needs to include a ROM into which the interleave read addresses is written with respect to the respective data rates, in order to perform the interleaving. When the data rate is variable as stated above, the ROM has an increased amount of the data to stored therein, thus the ROM needs to have an increased capacity.
As described in the foregoing, the prior art interleaver uses the ROM into which the interleave read address is written with respect to each data rate, thereby resulting into an increase in cost. In particular, when the CDMA PCS mobile station is operated based on the Standard SP-3384, the ROM should needs increased capacity, consequently raising a problem of an increase in cost.
An exemplary data interleaver is provided by U.S. Pat. No. 5,659,580 to Andrzej F. Partyka entitled
Data Interleaver For Use With Mobile Communications Systems And Having A Contiguous Counter And Address Twister.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a simple interleave read address generator composed of counters and logic gates.
According to an aspect of the present invention, an interleave read address generator includes a base-18 counter for counting a clock input on a base 18, to generate column address bits, a base-32 counter being enabled in response to a carry output from the base-18 counter, for counting the clock input on a base 32 to generate row address bits, and a multiplexer for changing a position of output bits of the base-32 counter according to data rate selection signals, to variably generate the row address bits.
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Bushnell, Esq Robert E.
Samsung Electronics Co,. Ltd.
Tzeng Fred F.
Yoo Do Hyun
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