Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2005-10-18
2005-10-18
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S005000, C711S127000, C711S217000, C365S230030, C365S230040
Reexamination Certificate
active
06957310
ABSTRACT:
Counter control section101increments a row number and column number on a two-dimensional array for a block interleave expressed by a matrix two-dimensional array, outputs the incremented numbers as the read address values, bit inversion apparatus102performs bit inversion using the read address values as inputs, column conversion section103outputs the address values corresponding to the bit inversion output values and the column numbers from counter control section101as the column conversion values, shift register104bit-shifts the output values of bit inversion apparatus102and outputs as the address offset values, adder106adds up the address offset values and column conversion values and size comparison section106compares the addition value with the interleave size and outputs data which is not greater than the interleave size as address values.
REFERENCES:
patent: 5502696 (1996-03-01), Yoon et al.
patent: 6138262 (2000-10-01), Baek
patent: 6668343 (2003-12-01), Kim et al.
patent: 2002/0170016 (2002-11-01), Inoue et al
patent: 2003/0023909 (2003-01-01), Ikeda et al.
patent: 0660558 (1995-06-01), None
patent: 7212250 (1995-08-01), None
patent: 8293860 (1996-11-01), None
patent: 9102748 (1997-04-01), None
patent: 9511377 (1997-11-01), None
patent: 0035101 (2000-06-01), None
Japanese Office Action dated Apr. 2, 2002.
English translation of Japanese office Action.
Korean Office Action dated Jun. 28, 2003 with English translation.
“A Proposal for Turbo Code Interleaving” TSG-RAN Working Group 1 meeting #3, Mar. 22-26, 1999, Eskilstuna, Sweden, Motorola, pp. 1-8.
M. Eroz, et al.; “On design of prunable interleavers for turbo codes”, IEEE 49thVehicular Technology Conference, vol. 2, Jul. 1999, pp. 1669-1673.
Supplementary European Search Report dated Feb. 24, 2005.
“A New Low-Complexity Turbo Code Interleaver Employing Linear Congruential Sequences,” TR45.5.3.1/98.12.08.08, XP 002237239 pp. 1-14, Dec. 8, 1998.
Nortel Networks, NTTDoCoMo, “Prime Interleaver Complexity Analysis,” TDOC R1-99-0513 of 3GPP TSG RAN WG 1, Meeting 4, XP002315002, pp. 1-0, Apr. 18, 1999.
Motorola, “A Proposal for Turbo Code Interleaving,” TDOC R1-99-0239 of 3GPP TSG RAN WG 1, Meeting 3, XP002315003, pp. 1-8, Mar. 22, 1999.
Eroz, M. et al., “On the Design of Prunable Interleavers for Turbo Codes,” Proc. of Vehicular Technology Conference, Houston, TX, vol. 2, XP010342111, ISBN 0-7803-5565-2, pp. 1669-673, May 16, 1999.
Ikeda Tetsuya
Yamanaka Ryutaro
Namazi Mehdi
Padmanabhan Mano
Stevens Davis Miller & Mosher LLP
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