Interface for high speed memory

Details Interface for high speed memory Interface for high speed memory

1997-07-18

1999-06-01

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

711168, 711169, 365194, 365193, G06F 1200

Patent

active

059097019

ABSTRACT:
An interface circuit, which can form part of a memory device or a memory controller, includes a read circuit, a write circuit, and a clocking circuit. The read circuit includes two registers or latches that receive alternate data read from burst EDO or synchronous memory. A multiplexer and read output register provide the data to a CPU or other application. If the memory is burst EDO, then the clocking circuit receives the system clock signal and generates a CAS signal based on positive or negative going edges of the clock signal, depending upon delays inherent in the system in which the present invention is employed. The CAS signal is then used to drive the two read latches. If the memory is synchronous memory, then the clock circuit includes an inverter that inverts the clock signal, and provides the inverted clock signal to the synchronous memory. The inverted clock signal is delayed and then used to drive the two read registers. A write register in the write circuit is driven based on the system clock, and therefore operates separately from the read circuit.

REFERENCES:
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patent: 5479646 (1995-12-01), Proebsting
patent: 5692165 (1997-11-01), Jeddeloh et al.
patent: 5721859 (1998-02-01), Manning
"PT86C521 V1-LS Pentium Processor PCI System Controller," Preliminary Data Book v0.7, Pico Power, Sep. 1995, pp. 1-45 through 1-67.
"Vesuvius-LS," Preliminary Data Book v0.7, Pico Power, Sep. 1995, pp. i-xiv.
Burst EDO DRAMs Comparative Description and System Design Guide, Micron Technology, Inc., 1995, pp. 1-27.
Burst EDO DRAM Information Data Sheets and Technical Notes, Micron Technology, Inc., 1995, pp. 1-14.

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