Interleave memory control apparatus and method

Details Interleave memory control apparatus and method Interleave memory control apparatus and method

1998-04-08

2000-10-10

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711 5, 711157, 711170, 711173, 36223004, G06F 1200

Patent

active

061311464

ABSTRACT:
A high multiplexing degree or interleaving factor is achieved in a memory having banks of different capacities. A group judging circuit generates the relevant interleave group and addresses in such group on the basis of the start address and sub-bank number of each interleave. A bank selection circuit generates a sub-bank number and addresses in the sub-bank on the basis of the address in the group. A multiplier and adder generate addresses in the bank on the basis of the addresses in the sub-bank.

REFERENCES:
patent: 5522059 (1996-05-01), Marushima et al.
patent: 5530837 (1996-06-01), Williams et al.
patent: 5668974 (1997-09-01), Grassi et al.
patent: 5924111 (1999-07-01), Huang et al.
Cheung et al. Design and analysis of a gracefully degrading interleaved memory system, IEEE Transactions on Computers, vol. 39(1) (Jan. 1990): 63-71.

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