Interleaved memory device for burst type access in...

Details Interleaved memory device for burst type access in... Interleaved memory device for burst type access in...

2001-01-31

2003-07-01

Yoo, Do Hyun (Department: 2187)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

C711S157000, C365S230090, C365S239000, C365S230030, C365S233500, C365S233100, C365S230020

Reexamination Certificate

active

06587913

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to memory devices, and, in particular, to an interleaved memory readable in a synchronous mode by successive locations with a sequential type of access commonly referred to as burst mode, and to a standard memory read in a random access asynchronous mode with fast access times.
BACKGROUND OF THE INVENTION
In a standard memory a read cycle is defined from a request of data effected by way of the input of a new address to the final output of the bits stored in the addressed location (byte, word, etc.). Internally, the reading process evolves through several steps. These steps include the acquisition of the new address to their decoding, to the generation of synchronizing pulses of the sensing circuits, to the output of the read data, and the like. The fundamental steps of a read cycle and the typical control signals that are used for managing it are depicted in FIG.
1
.
The ATD (Address Transition Detection) signal recognizes a change of the address input by the external circuitry and, therefore, the new access request initiates a new read cycle. After enabling the sense amplifiers by way of the signal SAenable, an equalization of the sensing circuitry takes place at the end of which, as timed by the signal EQZ, the effective reading of the memory cells takes place. Finally, after a certain interval of time that may vary from device to device, by way of a signal SAlatch, the recording of the read data into the latches in cascade to the sense amplifiers takes place. This is from where the read word may be transferred to the output buffers.
In memory devices designed for a synchronous read mode with a sequential type (burst) of access, the reading process exploits the fact that the reading takes place by successive locations. That is, the subsequent memory location to be read and, therefore, its address is predictable from the address of the location being currently read. A subgroup of these sequential (burst) synchronous read mode memories is represented by the so-called interleaved memories. A burst access interleaved memory is described in U.S. Pat. No. 5,559,990, for example.
In this type of memory, the cell array is divided in two semi-arrays or banks, each having its own read circuitry. The read streams of the two banks are thereafter superimposed though, according to one of the most commonly followed approaches. They are outphased from each other, while on one of the two banks or semi-arrays the steps of evaluation and transfer of the data to the output are being performed. On the other bank or semi-array (the next location to be addressed) a new read cycle may be started without waiting for the conclusion of the current read cycle that involves the first semi-array.
In interleaved memories, a basic scheme of which is depicted in
FIG. 2
, the array is divided in two independent banks or semi-arrays, EVEN and ODD, respectively, each having its own independent read path. Typically, there are two counters, one for each bank, containing the address of the currently pointed memory location. In case of simultaneous reading processes evolving respectively on the two semi-arrays, the least significant bit of the address (A
0
) supports the multiplexing between the EVEN and the ODD banks. If A
0
=0, the data coming from the EVEN semi-array will be made available at the output. If A
0
=1, the data coming from the ODD semi-array will be made available at the output.
As it is commonly known, the reading of the two semi-arrays is carried out according to one of two different approaches: simultaneous readings and multiplexing of the outputs; or time outphased readings.
According to the first approach, the readings are simultaneous on the two banks. The data read are stored in respective output registers and made available to the outside world in synch with an external clock signal. According to the second approach, the readings on the two semi-arrays have an alternate and interleaved evolution on a time base.
The first approach, though offering a simpler hardware implementation, limits the minimization of the start times of synchronous read cycles. For a better comprehension, it is necessary to consider the basic steps that are performed when passing from an asynchronous read mode to a synchronous read mode. With reference to the scheme of
FIG. 2
, and supposing a start of the reading from an address X, the latter will be loaded on the EVEN bank counter and on the ODD bank counter, less the least significant bit (A
0
) of the address. The two counters will point to the same location X of the respective bank or semi-array.
If A
0
=0: the first read data is relative to the address X of the bank EVEN and the successive read data is the data X of the bank ODD.
If A
0
=1: the first read data is relative to the address X of the bank ODD and the successively read data is relative to the X+1 address of the bank EVEN.
In the first case, it is sufficient to perform a simultaneous reading of the two banks and multiplex the outputs. In the second instance, it is necessary to increment the counter before starting the reading on the bank EVEN.
Usually, known synchronous memory devices do not make any initial increment and wait for the successive cycle for incrementing both counters, and therefore, read the location X+1 of the banks EVEN and ODD. This makes the times of the first read cycle and of the second sequential read cycle at best equal to the asynchronous read mode time of the memory.
In general, it may be stated that the efficient management of the read processes has a direct influence of the performance of the memory device. Many read path architectures have been proposed. Known read path architectures have generally been conceived for responding efficiently to either one or the other of the two modes of operation: asynchronous or synchronous.
If a memory device is designed to be read in an asynchronous mode, it will be generally provided with a rather simple control circuitry of the read data streams. This allows for the use of adaptive structures, such as dummy wordlines and dummy sense amplifiers, while leaving the reading circuitry free to evolve as fast as possible to achieve the shortest asynchronous access delays.
In contrast, in memory devices designed to function in a burst access mode or in a synchronous read mode, the possibility of making available in output a certain number of words read and stored in advance, permits, after a first asynchronous access, as long as it may be, a series of extremely fast read cycles. In this case though, the control logic must intervene heavily to manage the sense amplifiers which should not be left to evolve freely but be enabled, equalized and read at precise instants established by the control system. Prior European Patent Application Serial No. EP-98830801, filed on Dec. 30, 1998, and Italian Patent Application Serial No. MI99A00248, filed on Nov. 26, 1999, describe burst mode EPROM devices with the above characteristics. These patent applications are both incorporated herein by reference in their entirety, and are assigned to the assignee of the present invention.
SUMMARY OF THE INVENTION
An object of the present invention is provide a multipurpose memory device that can be used in a broader range of applications, whether requiring the reading of data from the memory in an asynchronous mode with random access (as in a standard memory) or the reading of data from the memory in a synchronous mode with sequential or burst type access. The multipurpose memory device should be capable of recognizing the mode of access and the reading that is currently required by the microprocessor. The multipurpose memory device should also self-condition its internal control circuitry as a function of such a recognition in order to read data in the requested mode without requiring the use of additional external control signals and/or implying a penalization in terms of access time and reading time of data compared to those which, for the same fabrication techn

Affiliated with

Also associated with

Rating

Interleaved memory device for burst type access in... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Interleaved memory device for burst type access in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Interleaved memory device for burst type access in... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3062791