Interleaver for iterative decoder

Details Interleaver for iterative decoder Interleaver for iterative decoder

2008-04-15

2008-04-15

Bataille, Pierre (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S005000, C711S211000, C711S218000, C711S219000, C710S053000, C341S081000, C341S155000, C341S161000, C375S265000

Reexamination Certificate

active

11231635

ABSTRACT:
Interleaver for iterative decoder. A memory management scheme allows for single plane/single port memory devices to be used by the interleaver. The design is adaptable to soft-in soft-out (SISO) decoders that perform iterative decoding. The interleaver may be implemented within communication devices that implement two distinct SISOs that operate cooperatively or within communication devices that employ a single SISO (in a recycled embodiment) that functionally performs the analogous decoding operations that would be performed by the two distinct SISO implementation. The use of single plane/single port memory devices by the interleaver allows for a great deal of savings from many perspectives: the sizes of the required interleaver memory and the interleaver pattern memory are both cut in half using this approach, and a cost savings may also be realized, in that, cheaper, slower memories may be used since each respective interleaver memory is read only every other cycle.

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