Interfacing an L2 cache to a single bus having alternative proto

Details Interfacing an L2 cache to a single bus having alternative proto Interfacing an L2 cache to a single bus having alternative proto

1997-04-15

1999-01-12

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

711117, G06F 1336

Patent

active

058600817

ABSTRACT:
A highly integrated central processing unit employs a single external physical bus having first and second protocols to support an L2 cache and a general purpose peripheral interface respectively, to avoid bond-out of the CPU bus to the external world and to steal unused bandwidth for L2 cache accesses while maintaining a standard peripheral bus interface.

REFERENCES:
patent: 5193163 (1993-03-01), Sanders et al.
patent: 5276852 (1994-01-01), Callander et al.
patent: 5384737 (1995-01-01), Childs et al.
patent: 5410669 (1995-04-01), Biggs et al.
patent: 5493655 (1996-02-01), Shen et al.
patent: 5535377 (1996-07-01), Parks
PCI Local Bus Specification, Rev. 2.0, Apr. 30, 1993, pp.16, 18, 69-77.
Microprocessor Report, "Intel's P6 Uses Decoupled Superscalar Design", by Linley Gwennap, Feb. 16, 1995, pp. 9-15.
Microprocessor Report, "Intel Unveils First PCI Chip Set", by Michael Slater, Dec. 9, 1992, pp. 9-12.
Microprocessor Report, "Digital Reveals PCI Chip Sets For Alpha", by Linley Gwennap, Jul. 12, 1993, pp. 20-22.
Microprocessor Report, "Local Buses Poised to Enter PC Mainstream", by Michael Slater and Mark Thorson, Jul. 8, 1992, pp. 7-13.
Hennessy & Patterson, "Computer Organization & Design The Hardware/Software Interface", Morgan Kaufmann Publishers, Inc., p. 559, 1994.
Micrsoft Press, "Microsoft Press Computer Dictionary: The Comprehensive Standard for Business, School, Library, and Home", pp. 181-182, 1994.

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