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Segmented content addressable memory array and priority encoder

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Segmented distributed memory module cache

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Segmented memory system employing different interleaving scheme

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Segmenting cache to provide varying service levels

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Segmenting cache to provide varying service levels

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Selectable block protection for non-volatile memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Selectable block protection for non-volatile memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Selectable block protection for non-volatile memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Selectable block protection for non-volatile memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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Selectable two-way, four-way double cache interleave scheme

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Selecting a cache for a request for information

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Selecting a command to send to memory

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Selecting basis functions to form a regression model for...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Selecting basis functions to form a regression model for...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Selecting erase method based on type of power supply for flash E

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
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Selecting storage clusters to use to access storage

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Selecting storage clusters to use to access storage

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
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Selective cache line allocation instruction execution and...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Selective coherency control

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
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Selective conflict write flush

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
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