Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2008-03-18
2008-03-18
Kim, Hong (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S133000, C711S134000, C714S701000, C714S702000, C714S704000, C714S718000, C702S108000, C702S119000, C702S120000
Reexamination Certificate
active
07346736
ABSTRACT:
One embodiment of the present invention provides a system that selects bases to form a regression model for cache performance. During operation, the system receives empirical data for a cache rate. The system also receives derivative constraints for the cache rate. Next, the system obtains candidate bases that satisfy the derivative constraints. For each of these candidate bases, the system: (1) computes an aggregate error E incurred using the candidate basis over the empirical data; (2) computes an instability measure I of an extrapolation fit for using the candidate basis over an extrapolation region; and then (3) computes a selection criterion F for the candidate basis, wherein F is a function of E and I. Finally, the system minimizes the selection criterion F across the candidate bases to select the basis used for the regression model.
REFERENCES:
Gluhovsky, Vengerov and O'Krafka, by Sun Microsystems Laboratories, “Comprehensive Multivariate Extrapolation Modeling of Multiprocessor Cache Miss reates”, Jul. 2006, ACM Journal Name, vol. V.
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Busch John R.
Gluhovsky Ilya
Vengerov David
Kim Hong
Li Zhuo H.
Park Vaughan & Fleming LLP
Sun Microsystems Inc.
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