Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Patent
1998-01-26
2000-11-07
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
711154, 711158, 711135, 710 52, G06F 1200
Patent
active
061450626
ABSTRACT:
A method and apparatus of selectively flushing a conflicted write transaction from a memory controller. According to the method, a new transaction is received that identifies a memory address to which the transaction is directed. It is determined whether an address of the new transaction matches an address of any previously queued transaction. When a match occurs, the one previously queued transaction that matches the new transaction is flushed from queue.
REFERENCES:
patent: 5125083 (1992-06-01), Fite et al.
patent: 5432918 (1995-07-01), Stamm
patent: 5666494 (1997-09-01), Mote, Jr.
patent: 5903776 (1999-05-01), Larson
Chittor Suresh
Ku Joseph
Nag Prantik Kumar
Sah Suneeta
Cabeca John W.
Intel Corporation
Vital Pierre
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