Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-03-08
2005-03-08
Anderson, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S118000, C711S120000, C711S143000, C711S135000, C711S137000, C711S147000, C711S148000, C711S206000, C711S209000, C711S212000
Reexamination Certificate
active
06865646
ABSTRACT:
One embodiment of a distributed memory module cache includes tag memory and associated logic implemented at the memory controller end of a memory channel. The memory controller is coupled to at least one memory module by way of a point-to-point interface. The data cache and associated logic are located in one or more buffer components on each of the memory modules. This embodiment includes an option to segment the cache. When the cache is segmented, the cache line size is halved. The segmentation allows the entire cache to be accessed without doubling the amount of tag address storage locations. The non-segmented cache may be used for memory systems using a burst length of eight bytes, while the segmented cache may be used for memory systems using a burst length of four bytes.
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Anderson Matthew
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Li Zhuo H.
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