Selectable two-way, four-way double cache interleave scheme

Details Selectable two-way, four-way double cache interleave scheme Selectable two-way, four-way double cache interleave scheme

1996-11-14

1999-08-31

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711130, 711153, G06F 1208

Patent

active

059467100

ABSTRACT:
Method and apparatus for maximizing cache memory throughput in a system where a plurality of requesters may contend for access to a same memory simultaneously. The memory utilizes an interleaved addressing scheme wherein each memory segment is associated with a separate queuing structure and the memory is mapped noncontiguously within the same segment so that all segments are accessed equally. Throughput is maximized as the plurality of requesters are queued evenly throughout the system.

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Patterson and Hennessy, "Computer Organization and Design", 1994, pp. 481-486.

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