Segmented content addressable memory array and priority encoder

Details Segmented content addressable memory array and priority encoder Segmented content addressable memory array and priority encoder

2007-05-15

2007-05-15

Peikari, B. James (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

Reexamination Certificate

active

10773591

ABSTRACT:
A CAM includes a plurality of CAM blocks, each including an array of CAM cells divided into a plurality of segments, each array segment for storing a number of data values that are assigned the same priority, a plurality of block priority circuits, each having inputs to receive match signals from a corresponding CAM block and having outputs to generate a block index and priority of a matching data value in the corresponding CAM block assigned the highest priority, and a global priority and index circuit having inputs to receive the block indexes and associated priorities from the block priority circuits, and having an output to generate a device index and associated priority of the highest priority matching value.

REFERENCES:
patent: 5649149 (1997-07-01), Stormon et al.
patent: 6389507 (2002-05-01), Sherman
patent: 6937491 (2005-08-01), Park et al.
patent: 2002/0129198 (2002-09-01), Nataraj et al.
patent: 2004/0030803 (2004-02-01), Eatherton et al.
patent: 2005/0138279 (2005-06-01), Somasundaram

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